When I first learned about computer science at the age of 11 or so (and in 1982 or so) the first page of the text book put digital and analogue computers on what seemed to be an equal footing. And then proceeded to ignore the latter for the rest of the book. Apart from a few notable exceptions ( https://en.wikipedia.org/wiki/Phillips_Machine ) I've often wondered about analogue computing.
And a general lack of reconfigurability to solve general problems. There’s been interest in analog neural networks for a long time.
Those problems you mention are important in music synthesis where people could live with limited reconfigurability but reliability is at a premium: synth players in early touring bands (e.g. Yes) had to be electronics technicians and instruments have to survive being packed in boxes and transported everywhere. The Yamaha DX-7 made FM synthesis mainstream because digital FM synthesis was absolutely reliable.
At the end of my undergrad, I remember a UW professor being poached by intel to work on analogue computing research project, the chair of the department at the time said that it was an opportunity that might not ever happen again and he had to take. I don’t think it went anywhere (since I never heard of intel coming out with a product), but I at least knew there was an attempt.
Really interesting - if I understood the article correctly, they're simulating this on conventional hardware, so in order to get the proposed benefits, it would need to be implemented in some other electronic medium.
It’s not clear to me how this would ever be practical since it seems dependent on n^2 scaling.
You’ve got to wonder when you have an image generation demo why would you possibly have 64 x 64 pixel output as your demo?
If I’m understanding this properly to generate a 4K image, you need like 5 trillion point to point connections on the chip. Even if power use from the oscillators is zero that’s going to be an issue.
Yes I too am perplexed. I'm into audio synthesis so I feel I have somewhat better-than-average knowledge of oscillators, from the component or elementary mathematical level (depending on whether they're analog or digital) to complex interactions for fun and profit (frequency, phase, ring modulation).
These are cool results but I was disappointed not to find any discussion of where oscillator array technology stands today what the manufacturing challenges/opportunities might be. It seems like it would be prohibitively expensive for anything beyond minimal networks of a few hundred nodes that could be used in sensors. Even if you have perfectly consistent oscillators that synchronize to each other within very fine tolerances, wiring them up to each other is still a massive headache.
What they are trying to achieve is to demonstrate that the coupling approach works in a simulated physics environment (O(n^2) as you point out) so that they can then build CMOS circuits that create actual oscillators and then let the laws of physics do the computation. This is a very bold vision!
And anyone who has done an introductory course in VLSI design would know that capacitance (coupling) is something you usually want to get rid of. However, all kinds of amazing analog circuits have been developed over the decades that exploit coupling effects. So, their idea is not outlandish at all.
Which idea is not outlandish? Physical computing? I agree physical computing is a fascinating topic.
But specifically what they’ve simulated here? I don’t see how that would ever work in real life scaled up to any kind of real size.
I’m not criticizing them for starting out small. Lots of things can be proven with small models. I’m saying in principle, I don’t see how this will work unless there’s some fundamentally new technique that is currently not known about. Maybe they have some secret idea but they haven’t shown it here.
At 5k to 10k nodes aren't they in the ballpark of a single layer from a scaled up conventional model? Rather than scaling further presumably you could stack these. However for a physical implementation ~100M interconnects seems questionable to me (but I know next to nothing about hardware engineering TBF) so I wonder if they intend to move to a partially connected model similar to the gyroscopic model of computation that the article links to.
Do you mean that they may get away with less oscillators because of the decoder layer? Well there’s the rub isn’t it, the more work you have done by a software layer the less power you’ve proportionally saved by having it be done by physical computing.
But let’s spitball here what would you estimate would be needed in number of oscillators and interconnects for a 4K image?
Conventional image generators still have to process n^2 connections so I don't think that observation is a valid objection in and of itself.
One thing I'm unclear on is that their total parameter count scales similarly to conventional models but many of those conventional models incorporate convolutions. I wonder how interconnect count (as opposed to unique parameters) compares to performance?
As to 4k images, I'm not clear how much farther their current architecture would be expected to scale. Single layer networks aren't parameter efficient compared to deep networks; I'd naively assume that to also apply here. That said given their results so far with what amounts to a single layer the naive assumption begins to seem questionable.
Think of the models making progress on CIFAR-10, ImageNet, CelebA, etc. 15 years ago. They had issues too and weren't just scaled-up as is to the architectures we have today.
This method is cool and the post explains it well. It would, however, be good to get more detail on the energy efficiency they flag as their motivation: is this model actually more energy efficient than the comparators they highlight?
It seems like total parameter count is more or less on par with conventional approaches so any gains won't be from there.
We can implement coupled oscillators in hardware but are the couplings and frequencies programmable? If they're being streamed in I guess you'd still have a memory bandwidth bottleneck and associated energy usage. If not then the fair comparison is to a conventional model hardcoded in an ASIC which AFAIU is actually quite energy efficient.
Very cool work - refreshing to see a of different approach. I learned about Kuramoto oscillators many years ago from a book called Sync, by Steven Strogatz, which I highly recommend.
(Disclaimer, not my area of expertise.) It appears to be adjacent but more general. There's an entire collection of methods (including reservoir computing) that conceptually resemble or are based on physical systems in one way or another. This appears to be an attempt to develop a new method that natively takes place as a physical process that we could readily implement in hardware.
Those problems you mention are important in music synthesis where people could live with limited reconfigurability but reliability is at a premium: synth players in early touring bands (e.g. Yes) had to be electronics technicians and instruments have to survive being packed in boxes and transported everywhere. The Yamaha DX-7 made FM synthesis mainstream because digital FM synthesis was absolutely reliable.
You’ve got to wonder when you have an image generation demo why would you possibly have 64 x 64 pixel output as your demo?
If I’m understanding this properly to generate a 4K image, you need like 5 trillion point to point connections on the chip. Even if power use from the oscillators is zero that’s going to be an issue.
These are cool results but I was disappointed not to find any discussion of where oscillator array technology stands today what the manufacturing challenges/opportunities might be. It seems like it would be prohibitively expensive for anything beyond minimal networks of a few hundred nodes that could be used in sensors. Even if you have perfectly consistent oscillators that synchronize to each other within very fine tolerances, wiring them up to each other is still a massive headache.
But specifically what they’ve simulated here? I don’t see how that would ever work in real life scaled up to any kind of real size.
I’m not criticizing them for starting out small. Lots of things can be proven with small models. I’m saying in principle, I don’t see how this will work unless there’s some fundamentally new technique that is currently not known about. Maybe they have some secret idea but they haven’t shown it here.
Do you mean that they may get away with less oscillators because of the decoder layer? Well there’s the rub isn’t it, the more work you have done by a software layer the less power you’ve proportionally saved by having it be done by physical computing.
But let’s spitball here what would you estimate would be needed in number of oscillators and interconnects for a 4K image?
One thing I'm unclear on is that their total parameter count scales similarly to conventional models but many of those conventional models incorporate convolutions. I wonder how interconnect count (as opposed to unique parameters) compares to performance?
As to 4k images, I'm not clear how much farther their current architecture would be expected to scale. Single layer networks aren't parameter efficient compared to deep networks; I'd naively assume that to also apply here. That said given their results so far with what amounts to a single layer the naive assumption begins to seem questionable.
We can implement coupled oscillators in hardware but are the couplings and frequencies programmable? If they're being streamed in I guess you'd still have a memory bandwidth bottleneck and associated energy usage. If not then the fair comparison is to a conventional model hardcoded in an ASIC which AFAIU is actually quite energy efficient.